1. Field of the Invention
The present invention relates to a semiconductor test apparatus which executes a characteristic test of a device under test (DUT), an input-output circuit which receives/transmits a signal with respect to the DUT and an impedance matching circuit which can be connected with this input-output circuit, and more particularly to a semiconductor test apparatus suitable for a characteristic test of a DUT having a low output terminal driving capability, an input-output circuit and an impedance matching circuit provided in the semiconductor test apparatus.
2. Description of the Related Art
Prior to an explanation of the present invention, a configuration of a conventional semiconductor test apparatus will be first described with reference to FIG. 12. As shown in the drawing, a semiconductor test apparatus 100 which determines a DUT 10 as a test target includes, as a main configuration, a pattern generator 20 which generates a test pattern, an expected pattern or the like, a waveform formatter 30 which formats the test pattern from this pattern generator 20 into a test signal waveform, an input-output circuit 200 which transmits the test signal waveform formatted by the waveform formatter 30 to the DUT 10 and receives an output signal outputted based on the test pattern from the DUT 10, judging means (a pattern comparator) 40 which logically compares the output signal (a test result) outputted from the DUT 10 with the expected pattern from the pattern generator 20 to detect a match/mismatch so that a quality of the DUT 10 is judged, direct-current testing means 50 which has a voltage source (not shown) which applies a desired direct-current voltage to the DUT 10 or a current detecting portion (not shown) which detects a power supply current supplied to the DUT 10 to allow the judging means 40 to judge a quality of the DUT 10, and others.
Here, as shown in FIG. 13, the input-output circuit 200 has a driver Dr which supplies the test pattern from the waveform formatter 30 to the DUT 10, a comparator Cp which receives an output signal from the DUT 10 and supplies it to the judging means 40, a resistance Rp which is an output load of this comparator Cp, and others.
It is to be noted that a part including the driver Dr, the comparator Cp and others will be referred to as a tester portion 60.
Further, in the input-output circuit 200, the driver Dr, the comparator Cp and the DUT 10 are connected with each other through a transmission line 70. As the transmission line 70, there is usually employed a coaxial cable having an impedance Zo=50Ω and a length of several-ten cm to several m.
Various kinds of technologies concerning such an input-output circuit 200 have been conventionally proposed (see, e.g., International Publication WO 03/008985).
It is to be noted that an output pin of the DUT 10 is modelized by using an ideal driver and an internal resistance.
Meanwhile, the DUT 10 which is a test target of the semiconductor test apparatus 100 has been recently diversified. For example, there are a DUT having a very low power consumption like an IC for a clock or a DUT which is not destroyed even if a high voltage such as 20 V is applied thereto like a semiconductor for an automobile.
Among others, a lower-power-consumption type DUT tends to be designed in such a manner that its output driving capability is intentionally lowered in order to reduce a power consumption. In such a DUT, a current intake/discharge capability is limited to a predetermined level. Therefore, when the DUT is to drive a 50-Ω type transmission line, i.e., a low impedance transmission line, this current limit is effected, and the DUT behaves as if an internal resistance is suddenly increased. In such a case, a correct waveform cannot be observed on a tester side.
Thus, in order to avoid this problem, it was possible to redesign the tester side of the semiconductor test apparatus to correspond to the low-power-consumption type DUT. However, there is a problem that a research/development cost or a manufacturing cost is increased.
Therefore, as a method of coping with the low-power-consumption type DUT at a low cost, there is used as a method which inserts a current limit resistance Rir to the outside of the DUT 10 as shown in FIG. 14 (a first prior art), for example.
According to this configuration, the DUT 10 can drive a transmission line as long as the current limit in the DUT 10 is not affected.
Furthermore, as another method, as shown in FIG. 15, there can be considered of controlling a switch SW1 in a tester portion 60 to disconnect a terminating resistance Rp (a second prior art) from the transmission line.
As a result, a high-impedance termination rather than a 50-Ω termination is provided, and a voltage supplied from the DUT 10 can be directly transmitted to a comparator Cp in a tester portion 60.
However, the first prior art has a problem that inserting the current limit resistance Rir causes an amplitude of a signal output from the DUT 10 to be divided by the current limit Rir and an impedance Zo of the transmission line 70, and hence a small amplitude must be detected on the tester side.
Moreover, the second prior art has a problem that a high impedance at both ends of the transmission line 70 generates multipath reflection, a long time is required for a waveform to be converged, and a test with a high speed/a high timing accuracy becomes difficult.